Search Results - michael+riera

4 Results

Sort By:

  1. Hardware-Agnostic Message Passing Interface for Heterogeneous Computing Systems
    Today's high-performance computing (HPC) systems are largely structured based on traditional central processing units (CPUs) with tightly coupled general-purpose graphics processing units (GPUs, which can be considered domain-specific accelerators). GPUs have a different programming model than CPUs and are only efficient in exploiting spatial parallelism...
    Published: 4/4/2025
    Inventor(s): Michael Riera, Fengbo Ren, Masudul Quraishi, Erfan Bank Tavakoli
    Keywords(s):  
    Category(s): Computing & Information Technology, Physical Science
  2. Stand-Alone Accelerator Protocol (SAP) for Heterogeneous Computing Systems
    Today's high-performance computing (HPC) systems are largely structured based on traditional central processing units (CPUs) with tightly coupled general-purpose graphics processing units (GPUs, which can be considered domain-specific accelerators). GPUs have a different programming model than CPUs and are only efficient in exploiting spatial parallelism...
    Published: 4/4/2025
    Inventor(s): Michael Riera, Fengbo Ren, Masudul Quraishi, Erfan Bank Tavakoli
    Keywords(s):  
    Category(s): Computing & Information Technology, Physical Science
  3. Software-Defined Board Support Package (SW-BSP) for Stand-Alone Reconfigurable Accelerators
    Today's high-performance computing (HPC) systems are largely structured based on traditional central processing units (CPUs) with tightly coupled general-purpose graphics processing units (GPUs, which can be considered domain-specific accelerators). GPUs have a different programming model than CPUs and are only efficient in exploiting spatial parallelism...
    Published: 4/4/2025
    Inventor(s): Michael Riera, Fengbo Ren, Masudul Quraishi, Erfan Bank Tavakoli
    Keywords(s):  
    Category(s): Computing & Information Technology, Physical Science
  4. High Performance Computing Framework for Accelerating Sparse Cholesky Factorization on FPGAs
    ­Solving large symmetric sparse linear systems using sparse Cholesky factorization plays a pivotal role in many scientific computing and high-performance computing (HPC) applications. The existing computational solutions to sparse Cholesky factorization based on CPUs and GPUs suffer from very limited performance for to two primary reasons. First,...
    Published: 2/13/2025
    Inventor(s): Erfan Bank Tavakoli, Fengbo Ren, Michael Riera, Masudul Quraishi
    Keywords(s): Algorithm Development, PS-Computing and Information Technology
    Category(s): Computing & Information Technology, Physical Science

Search Inventions

Looking for a technology or invention to commercialize? Arizona State University has more than 300 technologies available for licensing. Start your search here or submit your own invention.